Beyond the NanoSheet: The Architecture of the 1nm Node
As of March 2026, the semiconductor industry has reached a fundamental inflection point. While the transition from FinFET to Gate-All-Around (GAA) nanosheet transistors—pioneered at the 3nm and 2nm nodes—provided a temporary reprieve from the limitations of electrostatic control, the logic density roadmap now faces a structural wall. Standard cell scaling is no longer limited solely by gate pitch or metal pitch, but by the lateral separation required between n-type and p-type transistors.
The solution emerging in leading-edge R&D at IMEC and transitioning into pilot lines at TSMC (A10) and Intel (10A) is the Complementary FET (CFET). By stacking the n-FET and p-FET vertically rather than placing them side-by-side, the industry is moving toward a true 3D logic architecture that promises a 35% to 50% reduction in standard cell area.
The Geometric Imperative: Why Stack Transistors?
In a conventional nanosheet cell, the n-FET and p-FET are separated by a finite gap to allow for isolation and independent threshold voltage ($V_{th}$) tuning. This n-to-p separation consumes a significant portion of the cell's horizontal footprint. In a 6T (six-track) or 5T library, this separation prevents further shrinking of the cell height.
"The CFET effectively eliminates the n-to-p horizontal spacing bottleneck by folding the p-FET on top of the n-FET. This allows for the realization of a 4-track (4T) cell height, which was previously deemed physically impossible due to routing congestion and isolation requirements."
By collapsing the horizontal footprint, CFETs enable a massive leap in transistor density per square millimeter ($MTr/mm^2$) without requiring a proportional shrink in the Critical Dimension (CD) of the lithography. This is critical as we approach the physical limits of High-NA EUV (0.55 NA) patterning.
Monolithic vs. Sequential CFET Fabrication
There are two primary pathways to achieving a CFET structure, each presenting a distinct set of engineering trade-offs regarding thermal budgets and epitaxial quality.
1. Monolithic CFET
In the monolithic approach, all active layers (silicon and silicon-germanium) are grown epitaxially on a single starting wafer.
- Process Flow: Alternating layers of Si and SiGe are deposited to form the channel materials for both the bottom and top FETs.
- Challenges: The primary difficulty lies in the high-aspect-ratio (HAR) etching required to define the gate stack across both devices. Etching through a 100nm+ stack of sacrificial layers with nanometer precision requires extremely high selectivity in the Atomic Layer Etching (ALE) processes.
- Trade-off: It offers the highest density and lowest parasitic resistance but demands unprecedented control over epitaxial growth to prevent lattice defects across the thick multi-layer stack.
2. Sequential (Layer-to-Layer) CFET
Sequential CFET involves fabricating the bottom FET, then bonding a second thin-film silicon layer on top via Low-Temperature Wafer Bonding, followed by the fabrication of the top FET.
- Process Flow: The bottom device is processed up to the contact level. A top Si layer is transferred via a SmartCut or similar bonding process.
- Thermal Budget Constraints: This is the critical failure mode. The top device's processing temperature must remain below ~500°C to prevent the dopant diffusion or silicide degradation of the bottom device. This necessitates the use of novel Solid Phase Epitaxy (SPE) or laser annealing for dopant activation.
- Trade-off: It allows for different channel materials (e.g., a Ge p-FET on a Si n-FET) but introduces alignment risks between the top and bottom layers during bonding.
Overcoming Parasitic Capacitance and Resistance
One of the most significant hurdles in CFET implementation is the management of parasitic capacitance ($C_{gg}$). Stacking two gates on top of each other, separated by only a thin dielectric, creates a massive capacitive load that can negate the performance gains of the shorter interconnects.
Middle-of-Line (MOL) Complexity
In a CFET, the Middle-of-Line layers must contact both the top and bottom source/drain regions independently. This requires:
- Dual-Damascene Contact Vias: Vias of different depths that must land precisely on the lower S/D epitaxy without shorting to the upper S/D.
- Dielectric Isolation: The use of Low-k spacers (e.g., SiOCN or SiBCN) is mandatory to reduce the internal fringe capacitance between the gate and the S/D contacts.
Benchmarks at the 1nm node suggest that without optimization, CFETs could suffer a 15% frequency penalty due to RC delay, despite the area scaling. Engineers are counteracting this with Inner Spacer engineering—depositing a dielectric layer between the gate and the source/drain to shield the electric field.
The Role of Backside Power Delivery (BSPDN)
CFETs are essentially incompatible with traditional front-side power delivery. The routing congestion in a 4T CFET cell is so severe that there is no room for power rails (Vdd and Vss) on the front side of the wafer.
As a result, Backside Power Delivery Network (BSPDN)—often referred to as Intel’s PowerVia or TSMC’s A16/A10 backside rails—is a prerequisite for CFETs. By moving the power delivery to the back of the wafer and connecting to the transistors through Through-Silicon Vias (TSVs) or Nano-TSVs:
- IR Drop Reduction: Power loss is reduced by 25-30% because the power path is significantly shorter and utilizes larger, lower-resistance metal lines.
- Area Scaling: Removing the power rails from the front side frees up ~20% of the routing area, allowing the CFET stack to be even more compact.
Benchmarking 1nm CFET vs. 2nm NanoSheet
| Metric | 2nm NanoSheet (Base) | 1nm CFET (Projected) |
|---|---|---|
| Logic Density | 1.0x | 1.8x - 2.1x |
| Standard Cell Height | 5T (Track) | 3.5T - 4T |
| Effective Drive Current ($I_{eff}$) | 1.0x | 1.15x |
| Parasitic Capacitance ($C_{para}$) | 1.0x | 1.35x (unoptimized) |
| Operating Voltage ($V_{dd}$) | 0.7V - 0.75V | 0.6V - 0.65V |
Thermal Management: The Stacking Penalty
A primary concern for reliability engineers is the Thermal Resistance ($R_{th}$). In a CFET, the bottom transistor is effectively buried under the top transistor and multiple layers of interlayer dielectric (ILD).
"Heat dissipation becomes a first-order design constraint. The bottom FET operates at a significantly higher junction temperature ($T_j$) because it lacks a direct thermal path to the heat sink. This accelerates Bias Temperature Instability (BTI) and electromigration in the lower contacts."
To mitigate this, researchers are exploring Diamond-like Carbon (DLC) liners and high-thermal-conductivity gap-fill materials. Furthermore, the use of Backside Cooling—where the backside power delivery network is also used as a heat spreader—is being investigated as a way to pull heat away from the buried bottom FET.
Metrology and Yield: Seeing the Stack
Fabricating a CFET requires atomic-scale precision across a 3D structure that is opaque to traditional top-down inspection tools. Critical Dimension Scanning Electron Microscopy (CD-SEM) is no longer sufficient for characterizing the gate-all-around wrap or the inner spacer thickness in the bottom FET.
The industry is shifting toward Scatterometry (Optical Critical Dimension - OCD) and High-Voltage 3D X-ray (CD-SAXS). These tools use X-ray diffraction patterns to reconstruct the 3D geometry of the stack, allowing engineers to detect defects like "bridge" shorts between the top and bottom S/D regions, which are the most common yield killers in CFET pilot lines.
Conclusion: The Road to Mass Production
The transition to CFET represents the most radical change in transistor architecture since the invention of the integrated circuit. It moves us away from planar thinking into a regime where the vertical dimension is the primary driver of Moore's Law.
While the 2nm node (scheduled for ramp-up in late 2025/early 2026) relies on established nanosheet techniques, the 1nm (10A/A10) nodes targeted for 2027-2028 will be the debut of CFET. The engineering hurdles—particularly HAR etching, low-temperature dopant activation for sequential stacks, and thermal management—are formidable. However, the density gains are non-negotiable for the next generation of AI accelerators and high-performance computing (HPC) silicon, where the demand for trillions of transistors on a single package continues to outstrip current manufacturing capabilities.