Beyond the Nanosheet: The Shift to CFET
As the industry matures at the 2nm (N2) and 1.4nm (A14) nodes, the traditional Gate-All-Around (GAA) nanosheet architecture is encountering a fundamental scaling wall: the cell-height bottleneck. While GAA nanosheets improved electrostatic control over FinFETs, they did not fundamentally change the planar layout of the nFET and pFET transistors. In a standard logic cell, these two transistors sit side-by-side, separated by a dummy gate or an isolation trench. This lateral separation consumes a significant portion of the standard cell area, preventing further reduction in track height.
Enter the Complementary FET (CFET). As of late 2026, research prototypes at the A7 (7-angstrom) node have demonstrated that by vertically stacking the nFET and pFET on top of each other, designers can effectively halve the active area of a logic gate. This transition is not merely an incremental improvement but a radical re-architecting of the CMOS process flow, shifting from a 2D lateral layout to a true 3D monolithic structure.
Monolithic vs. Sequential Architectures
There are two primary pathways to achieving CFET: Monolithic and Sequential (also known as 3D VLSI). As the industry moves toward high-volume manufacturing (HVM) for the A7 node, the trade-offs between these two approaches have become the central debate in semiconductor R&D.
1. Monolithic CFET
In the monolithic approach, both the n-type and p-type channels are formed during the same epitaxial growth process on a single wafer. This involves growing a complex superlattice of alternating Silicon (Si) and Silicon-Germanium (SiGe) layers.
- Advantages: Lower cost due to fewer lithography steps and no wafer-to-wafer bonding requirements. It eliminates the alignment issues associated with bonding separate wafers.
- Challenges: Extremely high aspect-ratio etching. Developing a replacement metal gate (RMG) process that can independently set the work functions for the top and bottom transistors within a confined vertical space is technically daunting.
2. Sequential CFET
Sequential integration involves processing the bottom transistor (typically the pFET) on one wafer, and then bonding a second thin layer of silicon on top to build the nFET.
- Advantages: Allows for different channel materials (e.g., Ge for pFET and Si for nFET) to optimize carrier mobility. It also provides more flexibility in the thermal budget for the top transistor.
- Challenges: The "thermal budget" problem. Processing the top transistor must be done at low temperatures (<500°C) to avoid degrading the silicides and junctions of the bottom transistor already in place.
Benchmark Comparison: At the A7 node, a Monolithic CFET inverter (INV) achieves a 42% area reduction compared to a GAA nanosheet inverter at the same performance target, while Sequential CFET offers a 45% reduction but at a 1.8x higher wafer cost.
The A7 Process Flow: Mastering the Stack
The fabrication of a monolithic CFET at the A7 node requires a precision never before seen in CMOS manufacturing. The process begins with the deposition of a Si/SiGe superlattice stack. For a typical CFET, this requires at least six to eight alternating layers to form the channels for both the top and bottom devices.
Critical Etch and Inner Spacers
The most significant hurdle is the inner spacer formation. In GAA, this was difficult; in CFET, it is an order of magnitude harder. Engineers must selectively etch back the SiGe layers from a high-aspect-ratio trench without damaging the Si nanosheets. This is followed by the atomic layer deposition (ALD) of a low-k dielectric to isolate the gate from the source/drain.
Dual Work Function Metal (WFM) Integration
Perhaps the most complex step is the Replacement Metal Gate (RMG) process. In a CFET, the gate must wrap around the top nFET and the bottom pFET. However, these transistors require different work function metals to set their respective threshold voltages ($V_{th}$).
- Bottom WFM Deposition: The entire cavity is filled with the p-type metal.
- Selective Etch-back: A sacrificial material is used to protect the bottom metal while the top portion is etched away.
- Top WFM Deposition: The n-type metal is deposited to wrap around the top nanosheets.
- Isolation: A middle dielectric isolation (MDI) layer must be placed precisely between the two transistors to prevent leakage.
Solving the Routing Crisis: Backside Power Delivery
Scaling the transistors to the A7 node is useless if the Back End of Line (BEOL) interconnects cannot deliver power and signals without massive IR drop. The CFET architecture is physically incompatible with traditional front-side power delivery because the stacked transistors leave no room for the massive power vias required.
This has mandated the universal adoption of Backside Power Delivery Networks (BSPDN). In this scheme, the signal routing remains on the front side of the wafer, while the power delivery (VDD and VSS) is moved to the backside.
- Buried Power Rails (BPR): These are thick tungsten or ruthenium rails buried below the transistor level, connecting directly to the backside power vias.
- Nano-Through Silicon Vias (nTSVs): These connect the BPR to the backside metal layers. Their aspect ratio must be tightly controlled to minimize parasitic resistance.
Performance Data: Implementing BSPDN in a CFET-based A7 design reduces IR drop by 35% and allows for a 15% increase in frequency due to reduced congestion in the front-side metal layers.
Materials Science: The Transition to Ruthenium
As the copper (Cu) interconnects reach their physical limits—where the electron mean free path is longer than the wire width—resistivity skyrockets. For the A7 node, the industry is pivoting toward Ruthenium (Ru) for the lower metal layers (M0 to M3).
Unlike copper, ruthenium does not require a thick diffusion barrier (like TaN/Ta), which occupies valuable conductive volume. At a 10nm line width, Ru exhibits lower effective resistance than Cu. Furthermore, Ru’s high melting point makes it more resistant to electromigration, a critical factor when current densities in CFET devices exceed $10^8 A/cm^2$.
Comparative Interconnect Resistivity at 10nm Width:
- Copper (with barrier): ~12.5 $\mu\Omega\cdot cm$
- Cobalt: ~10.2 $\mu\Omega\cdot cm$
- Ruthenium (barrierless): ~7.8 $\mu\Omega\cdot cm$
Thermal and Metrology Challenges
The 3D nature of CFET introduces a "thermal silo" effect. The bottom transistor is effectively insulated by the top transistor and the surrounding low-k dielectrics, making heat dissipation difficult. Self-heating becomes a major reliability concern, potentially leading to Bias Temperature Instability (BTI) and accelerated device aging.
From a metrology perspective, standard CD-SEM (Critical Dimension Scanning Electron Microscopy) cannot "see" through the stack. This has forced fab operators to rely on Scatterometry and high-energy In-line AFM (Atomic Force Microscopy) to monitor the profiles of the buried channels. Any variation in the nanosheet thickness at the bottom of the stack can lead to massive $I_{on}/I_{off}$ mismatches between the nFET and pFET.
The Path to A5 and Beyond
The implementation of CFET at the A7 node is the bridge to the A5 (5-angstrom) node, where we expect to see the integration of 2D materials like Molybdenum Disulfide ($MoS_2$) as the channel material. For now, the move to monolithic CFET represents the most significant shift in transistor topology since the introduction of the FinFET in 2011.
Engineers must balance the massive density gains—the move from 5-track (5T) to 3-track (3T) standard cells—against the yield risks inherent in such a complex 3D fabrication process. The success of A7 hinges not on the physics of the transistor itself, but on our ability to etch, fill, and connect these vertical structures at the atomic scale.
Summary of CFET Technical Specifications at A7:
- Contacted Poly Pitch (CPP): 40-44 nm
- Metal Pitch (MP): 16-18 nm
- Nanosheet Width: 12-20 nm
- Vertical Separation (n-to-p): 30-50 nm
- Standard Cell Height: 3T (~90-110 nm)
- Operating Voltage ($V_{dd}$): 0.6V - 0.7V